Getting Started

Calyx is an intermediate language and infrastructure for building compilers that generate custom hardware accelerators. These instructions will help you set up the Calyx compiler and associated tools. By the end, you should be able to compile and simulate hardware designs generated by Calyx.

Compiler Installation

Install Rust (it should automatically install cargo).

Clone the repository:

git clone https://github.com/cucapra/calyx.git

Then build the compiler:

cargo build

You can invoke the compiler in one of two ways:

cargo run -- --help # Rebuilds the compiler if the sources changed
./target/debug/futil --help # Default debug build of the compiler

Running Core Tests

The core test suites tests the Calyx compiler passes. Install the following tools for running the core tests:

  1. runt hosts our testing infrastructure. Install with: cargo install runt
  2. jq is a command-line JSON processor:
    • Ubuntu: sudo apt install jq
    • Mac: brew install jq
    • Other platforms: JQ installation

Build the compiler:

cargo build

Then run the core tests with:

runt -i core

If everything has been installed correctly, this should not produce any failing tests.

Installing the Command-line Driver

The Calyx driver wraps the various compiler frontends and backends to simplify running Calyx programs.

Install Flit:

pip3 install flit

Install fud (from the root of the repository):

flit -f fud/pyproject.toml install -s

Configure fud:

fud config global.futil_directory <full path to Calyx repository>

Check the fud configuration:

fud check

fud will report certain tools are not available. This is expected.

Simulating with Verilator

Verilator is the default simulation backend for Calyx. If you want to run your Calyx programs, you need to install Verilator.

On a Mac, install with:

brew install verilator

Otherwise, you will probably need to compile it from source yourself (the versions in Linux repositories are generally out of date). There instructions are stolen from Verilator's installation instructions:

git clone https://github.com/verilator/verilator
cd verilator
git pull
git checkout master
autoconf
./configure
make
sudo make install

Use fud to check you have the right version:

fud check

fud should report that the verilator binary was installed and has the right version. Some tools will be reported missing. This is expected.

Generating Simulation Results

By default, simulating with Verilator will produce a VCD file which is not human-readable. Our tests use vcdump to transform VCD file into JSON files.

Install vcdump:

cargo install vcdump

Use fud to check the right version was installed:

fud check

It should report that the vcdump binary is available and has the right version. Some tools will be reported missing. This is expected.

Running a Hardware Design

We're all set to run a Calyx hardware design now. Run the following command:

fud e examples/tutorial/language-tutorial-iterate.futil \
  -s verilog.data examples/tutorial/data.json \
  --to dat -v

This command will compile examples/tutorial/language-tutorial-iterate.futil to Verilog using the Calyx compiler, simulate the design using the data in examples/tutorial/data.json, and generate a JSON representation of the final memory state.

Congratulations! You've simulated your first hardware design with Calyx.

Where to go next?