The Capra lab is working on accelerator design languages (ADLs), higher-level languages that compile into hardware accelerators. Hardware accelerators can perform specialized computations more efficiently than general purpose compute via CPUs. With the decline of Moore’s Law, accelerators are increasingly needed to improve performance of critical applications. But currently, designing an accelerator involves writing code in low-level Hardware Description Languages (HDL) such as Verilog, which have a steep learning curve and are difficult to understand, diagnose problems, and debug. Our goal is to make the hardware design process more accessible to software engineers and domain experts by developing ADLs and engineering tools that operate at a higher level of abstraction than HDLs.
As part of the tooling, we are developing a profiler framework to help ADL developers speed up their programs. Like an ordinary software profiler, our new accelerator profiler aims to help engineers find opportunities to optimize their code. Even though profilers are an absolutely critical tool for performance engineering in software, as far as we know, there are no similar profilers for ADLs—so there’s an important opportunity here.
There are two different projects that start in Spring 2025. They require a commitment of at least 8 hours per week, either for credit or for pay. Depending on progress, there may be a possibility to continue and work full time over the summer.
We want to use hardware metrics in our profiler such as the area taken up by a design. One such metric is area usage, which indicates the physical resources that we need in our hardware. A designer usually obtains area usage information by providing HDL code to Electronic Design Automation (EDA) toolchains such as AMD’s commercial Vivado tools, which place and route a hardware design onto an FPGA and give users a performance report. The performance report also shows information at a finer granularity, but we need to provide users with actionable feedback at the level of the original ADL program. We are looking for an undergraduate student to design and develop a mechanism to obtain area usage data from Vivado tools, and propagate that information back to the ADL level. Ideally, you should have taken CS3110 or CS3410, although this is not a requirement. It would be extra awesome if you have experience developing for FPGAs! (but again, not a requirement)
An important research question that we are investigating is: “How are ADL profilers useful?”. We have a prototype profiler that provides cycle-level timing of ADL programs, and we’d like to perform case studies on how it can help ADL users optimize their programs. We are also looking to identify ADL optimization patterns, i.e. simple and common code changes that can be made to optimize ADL programs. Through this process, we’d also like to get user input on ways we can improve the user’s experience. We are looking for an undergraduate student to improve the cycle-level timing of ADL programs using results from the profiler. Ideally, you should have taken CS3110 or CS3410, although this is not a requirement.